gallo magnetix
MGB Mezzanine
Envelope Central
MGB dedicates a seperate high performance microcontroller to the task of generating 8 Envelope Generators. The VCO Pitch characteristic is generated by the MGB Host, the MGB Mezzanine Processor connects to a 12 channel 8 DAC integrated circuit and either directly or as the sum of additional envelopes control:
- VCO PWM (2) and LEVEL (2),
- VCF Frequency (2) and Q (2),
- VCA Level (2),
Envelopes to date.
Modulation Peripheral
The MGB Mezzanine Processor (MPP) is a board which seats a fast microcontroller to off load the MGB Host processor for the generation of 8 envelopes, a LFO and Random Noise. The capacity of the microcontroller is such that it can also drive a bit-mapped LCD and the 4 Potentiometer motors.
Looking to the MGB Host Processor as a byte wide "mail box", a command exchange not disimilar to a MIDI exchange specifies parameters for the MMP. This exchange is parallel however and implements a 9 bit FIFO allowing full byte data values and a single Command/Data Flag in the 9th bit.
The Mezzanine physically "plugs" onto and between the MGB MSC1211 Host Processor board and the Analog Motherboard, bridging the two.
Mezzanine Schematic
The connection to the Analog Motherboard allows the MMP to drive the 12 channel AD8804 DAC using an 4 wire serial interface. Each channel within the AD8804 dac connects to a specific input of a MGB synthesizer circuit (i.e. VCO/VCF/VCA). The control program for the Mezzanine modulators produces 8 envelope values depending upon the state of GATE On/Off commands.
Envelope generation originally was resident on the Host Processor, being an '8051 derivitive, the DS'420 easily executes the exact envelope code, so this component of the development is eased. The DS89C420 is In Circuit Programmable with a little support circuitry. In order to not duplicate this circuitry for every DS'420 project, a simple "programmer inteface" board is used and the MMP need only supply a connection point and some pull-up resistors.
Off Board Programmer Schematic
Envelope Execution Rate:
Using a 16MHz crystal and employing the DS'420 clock multiplier, a single clock instruction executes in 31.25 nS. Twelve DAC Channels can be updated in 49us. This period equals half of the time available for all computational Tasks at a 10kHz update rate. The remaining 51us amounts to approximately 1632 instructions. So every 100us 800 Modulation instructions (Env/LFO/Noise) execute and 800 Motor/LCD instructions execute. The FIFO interupts are "ad hoc" occurring with control change and Note On/Off states.
The DACs are fitted 1KHz 18-dB/8ve reconstruction filters which means at 10kHz these filters attenuate to ~60dB.
Modulator Core Routine
An envelope generators routine has a core comprised of a 24 bit Phase + Increment addition, a Sine Table Lookup, Evaluation, and Value Storage for Routing. This core executes in approximately 16 instructions (.5us).
Example envelope waveform.
Another envelope waveform.
Core Application: The core is wrapped inside a specific ADSR Mode. As an example, the Attack mode occurs for a Note Activation.
Attack mode: The Attack mode interrupts any other mode be it Decay, Sustain or Release. This "Re-Trigger" characteristic occurs for each new assigned Note Activation. The Attack value is derived by "riding" the up-slope from minimum to maximum (0-128) of the Sine Wave stored in the Sine Table. These samples are progressively read from the table with an index equal to the Current Phase (24 bit) plus Rate of Table Increment (also 24). Sine Table Values are stored for scaling and routing. Should the Sine Table Pointer equals or exceeds 128 (last positive Up-Slope table location), instead of reading a table value we "saturate" at Max Level, clear the Attack mode and start the Decay mode. Attack cycles that interrupt another mode, progresses upward, at the Attack Rate of Increment, from the current Decay, Sustain or Release value.
Decay and Release mode: Each of these modes "ride" the same Sine Table Slope but in the reverse or "down" direction. This is the negative going Maximum to Minimum value Direction. Each mode has it's own Rate of Increment and each "saturates" at minimum value when the Sine Table Pointers is equal or "less" than 0 (minimum Sine Value).
The Decay mode occurs only when we reach maximum Attack value. This means it always "starts" at the highest value location and decends down the table to minimum value. The Release mode occurs because a Note is Now OFF. This can occur at any time in Attack, Decay or Sustain modes. No matter what mode it terminates, it rides down from the current Table Value to minimum value at it's Rate of Increment. Fast note activations with slow Attack rates can mean the Decay mode never occurs because the Attack cycle was not over when the key was release.
Routing: Modulator Values are not output directly. The 12 DACS that connect to the MGB analog circuitry output a user specified value which is the sum of any or all modulations (plus static values). Each Modulator value can be adjusted or "scaled" prior to mixing with other Modulators. This is the Percent of Modulation or Modulation Level control which means each DAC (MGB control portal) has a 10 input mixer function in front of it.
As usual:
This is a project not a product and, this project is currently In Progress. The following page reflects the current stage of MG-B development. All device capability "claimed" is demonstrable is art.
Current MG-B Design Information:
VCO Detail
VCF Detail
VCA Detail
MIDI Control
